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| fn8923 rev.1.00 page 1 of 57 aug 17, 2017 fn8923 rev.1.00 aug 17, 2017 ISL8277M digital dc/dc pmbus 25a module datasheet the ISL8277M is a 25a step-down dc/dc power supply module with an integrated digital pwm controller, synchronous power switches, an inductor, and passives. only bulk input and output capacitors are needed to finish the design. the 25a of continuous output current can be delivered without a need of airflow or a heatsink. the ther mally enhanced hda module is capable of dissipating heat directly into the pcb. the ISL8277M uses chargemode? control architecture, which responds to a transient load within a single switching cycle. the ISL8277M comes with a preprogrammed configuration for operating in a pin-strap mode . output voltage, switching frequency, and device smbus address can be programmed with external resistors. more configuration such as soft-start and fault limits can be easily programmed or changed using the pmbus compliant serial bus interface. pmbus can be used to monitor voltages, current, temperatures, and fault status. the ISL8277M is supported by powernavigator? software, a graphical user interface (gui) that can be used to configure modules to a desired solution. the ISL8277M is available in a 41-pin compact 17mmx19mm hda module with very low profile height of 3.6mm, suitable for automated assembly by standard surface mount equipment. the ISL8277M is rohs compliant by exemption. features ? complete digital switch mode power supply -wide v in range: 4.5v to 14v -programmable v out range: 0.6v to 5v ? pmbus compliant i 2 c communication interface -programmable v out , margining, uv/ov, i out limit, soft-start/stop, sequencing, and external synchronization - monitor: v in , v out , i out , temperature, duty cycle, switching frequency, and faults ? chargemode control architecture ?1.0% v out accuracy over line, load, and temperature ? power-good indicator ? over-temperature protection ? internal nonvolatile memory and fault logging ? patented thermally enhanced hda package ? intuitive configuration via powernavigator applications ? server, telecom, storage, and datacom ? industrial/ate and networking equipment ? general purpose power for asic, fpga, dsp, and memory related literature ? for a full list of related documents, visit our website - isl87277m product page - figure 1. complete digital switch-mode power supply figure 2. small package for high power density note: 1. only bulk input and output capacitors are required to finish the design. ISL8277M v out vin vdd vout vsen+ vsen- v in pmbus interface vdrvin vdrvout c in c out 10 f salrt sda scl sgnd pgnd 10 f en enable vcc vr55 10 f 1 7 m m 3.6mm 1 9 m m fn8923 rev.1.00 aug 17, 2017
ISL8277M fn8923 rev.1.00 page 2 of 57 aug 17, 2017 table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ISL8277M internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 efficiency performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 transient response performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 derating curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 smbus communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 soft-start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 input undervoltage lockout (uvlo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 smbus module address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output prebias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 phase spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 monitoring via smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 snapshot parameter capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 nonvolatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pcb layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pcb layout pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 thermal vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 stencil pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 reflow parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 pmbus command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pmbus data formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pmbus use guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 pmbus command descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 firmware revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ISL8277M fn8923 rev.1.00 page 3 of 57 aug 17, 2017 ordering information part number ( notes 2 , 3 , 4 ) part marking temp range (c) package (rohs compliant) pkg. dwg. # ISL8277Mairz ISL8277Ma -40 to +85 41 ld 17x19 hda y41.17x19 ISL8277Meval1z evaluation board notes: 2. add ?-t? suffix for 500 unit or ?-t1? suffix for 100 unit tape and reel options. refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged prod ucts are rohs compliant by eu exemption 7c-i and 7a. they employ special pb-free material sets; molding compounds/die attach materials and ni pdau plate-e4 termination finish, which is compatible with both snpb and pb-free s oldering operations. intersil pb-free products are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free re quirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), see the product information page for ISL8277M . for more information on msl, see tech brief tb363 . isl xxxxm f t r z s intersil device designator base part number firmware revision a: fc01 operating temperature i: industrial (- 40c to +85c) shipping option blank: bulk t: tape and reel rohs z: rohs compliant package designator r: high density array (hda) ISL8277M fn8923 rev.1.00 page 4 of 57 aug 17, 2017 pin configuration ISL8277M (41 ld hda) top view vdrvout vin ddc ascr vsen - nc nc vsen+ nc pgnd vcc sync sgnd vout sgnd vswh pgnd pg ss/uvlo pgnd phase vdrvin nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 18 19 20 21 22 23 24 25 41 vr55 9 salrt nc nc en scl sda sa mgn vset sgnd pgnd vdd vddc v25 vr5 vr6 pin descriptions pin label type description 1 ddc i/o a digital-dc ? bus. this dedicated bus provides the communication channel between devices for features such as sequencing and fault spreading. the ddc pin on all digi tal-dc devices should be connected together. a pull-up resistor is required for this application. 2 ascr i chargemode control ascr parameters selection pi n. used to set ascr gain and residual values. 6 vsen+ i differential output voltage sense feedback. connect to positive output regulation point. 7 vsen- i differential output voltage sense feedback. connect to negative output regulation point. 8 vdrvout pwr output of internal regulator for powering internal mosfet driver. connect a 10f bypass capacitor to this pin. the regulator output is dedicated to powering internal mosfet drivers. do not use this regulator for any other purpose. for applications with vin less th an 5.2v, use an external 5v supply or connect this pad to vin. 9 vdrvin pwr input supply to internal regulator for powering internal mosfet drivers. connect this pad to vin. 10 vcc pwr bias pin for internal regulator. connect vcc pad to vr 55 pin directly with a short loop trace. not recommended to power external circuit. 11 vin pwr main input supply. refer to ? pcb layout guidelines ? on page 21 for the decoupling capacitors placement from vin to pgnd. 12, 23, 31, 34 pgnd pwr power ground. refer to ? pcb layout guidelines ? on page 21 for the pgnd pad connections and decoupling capacitors placement. 13 vswh pwr switch node. refer to ? pcb layout guidelines ? on page 21 for connecting vswh pads to electrically isolated pcb copper island to dissipate internal heat. ISL8277M fn8923 rev.1.00 page 5 of 57 aug 17, 2017 14 vout pwr power supply output. range: 0.6v to 5v. refer to the ? derating curves ? on page 12 for maximum recommended output current at various output voltages. 15, 27, 40 sgnd pwr controller signal ground. refer to ? pcb layout guidelines ? on page 21 for the sgnd pad connections. 16 vdd pwr input supply to digital controller. connect vdd pad to vin supply. refer to ? pcb layout guidelines ? on page 21 for the decoupling capacitors placement from vdd to sgnd. 17 en i external enable input. logic high enables the module. 18 scl i/o serial clock input. a pull-up resistor is required for this application. 19 sda i/o serial data. a pull-up resistor is required for this application. 20 salrt o serial alert. a pull-up resistor is required for this application. 21 sa i serial bus address select pin. refer to table 9 on page 19 for list of resistor values to set various serial bus address. 24 mgn i external v out margin control pin. active high (> 2v) signal at this pin sets v out margin high, active low (< 0.8v) sets v out margin low, and high impedance (float) will bring v out back to nominal voltage. factory default range for margining is nominal v out 5%. when using pmbus to control margin command, leave this pin as no connect. 25 vset i output voltage selection pin. refer to table 4 on page 17 for list of resistor values to set various output voltages. 28 pg o power-good output. power-good output can be an open drai n that requires pull-up resistor or push-pull output that can drive a logic input. 29 ss/uvlo i soft-start/stop and undervoltage lockout selection pin. used to set turn on/off delay and ramp time as well as input uvlo threshold levels. refer to table 5 and table 8 for list of resistors. 30 phase pwr switch node pad for dcr sensing. electrically shorted inside to vswh, but for higher current sensing accuracy connect phase pad to vswh pad externally. refer to ? pcb layout guidelines ? on page 21 . 35 vr6 pwr 6v internal reference supply voltage. 36 vr5 pwr 5v internal reference supply voltage. 37 vddc pwr vdd clean. noise at the vdd pin is filtered by an inte rnal ferrite bead and capacitor. for vdd > 6v, leave this pin as no connect. for 5.5 vdd 6v, connect the vddc pin to the vr6 pin. for 4.5 vdd < 5.5v, connect the vddc pin to the vr6 and vr5 pin. 38 v25 pwr 2.5v internal reference supply voltage. 39 sync i/o sync pin can be input to external clock for frequency synchronization or output to supply clock signal to other modules for synchronization. refer to table 6 on page 18 for list of resistor values to program various switching frequencies. 41 vr55 pwr internal 5.5v bias for internal regulator use only. connect vr55 pin directly to vcc pin. not recommended to power external circuit. 3, 4, 5, 22, 26, 32, 33 nc these are test pins and are not electrically isolated. leave these pins as no connect. pin descriptions (continued) pin label type description ISL8277M fn8923 rev.1.00 page 6 of 57 aug 17, 2017 ISL8277M internal block diagram figure 3. block diagram digital controller sgnd vset scl salrt sa en pg sync sgnd pwm out pmbus/i 2 c interface sda adc-10 csa vsa supervisor internal temp sensor protection oc/uc d-pwm pll sync out power management ss margining ov/uv interleave sequence nvm vdd ddc snapshot fault spreading ot/ut vout 0.3 h logic vin pgnd regulator driver and fets vin vdrvin vdd v sen+ v sen- mgn adc-10 vr55 vr5 ldo vr6 vddc fb pgnd 332 chargemode control ?? v25 ss/uvlo ascr vcc vdrvout vdrvout ISL8277M fn8923 rev.1.00 page 7 of 57 aug 17, 2017 absolute maximum rating s thermal information input supply voltage, vin pin . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v input supply voltage for controller, vdd, vddc pin. . . . . . . . . -0.3v to 17v input gate driver supply voltage, vdrvin pin . . . . . . . . . . . . . -0.3v to 17v output voltage, vout pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v output gate driver supply voltage, vdrvout pin . . . . . . . . . . . -0.3v to 6v switch node referenced to pgnd pin, vswh pin . . . . . . . . . -0.3v to 25v switch node for dcr sensin g referenced to sgnd pin, phase pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 25v input bias voltage for internal regulator, vcc pin . . . . . . . . -0.3v to 6.5v 6v internal reference supply voltage, vr6 pin . . . . . . . . . . . -0.3v to 6.6v internal reference supply voltage, v r5 , vr55 pin . . . . . . . . -0.3v to 6.5v 2.5v internal reference supply voltage, v25 pin . . . . . . . . . . . -0.3v to 3v logic i/o voltage for ddc, en, mng, pg, ascr, sa, scl, sda, salrt, sync, ss/uvlo, v set . . . . . . . . . . . -0.3v to 6.0v analog input voltages for vsen+, xtemp+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v vsen-, xtemp- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v esd rating human body model (tested per js-001-2014) . . . . . . . . . . . . . . . . 2000v machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per js-002-2014) . . . . . . . . . . . . . . 750v latch-up (tested per jesd78e; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 41 ld hda package ( notes 5 , 6 ) . . . . . . . . 7.5 2.2 maximum junction temperature (plastic package) . . . . . . . . . . . .+125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to figure 31 recommended operating conditions input supply voltage range, v in . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 14v input supply voltage range for controller, v dd . . . . . . . . . . . 4.5v to 14v output voltage range, v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.6v to 5v output current range, i out(dc) ( note 9 ) . . . . . . . . . . . . . . . . . . . . 0a to 25a operating junction temperature range, t j . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ? ja is measured in free air with the module mounted on an evaluation board 3 x 4.5 inch in size with 2oz surface and 2oz buried plan es and multiple via interconnects as specified the ISL8277Mev al1z evaluation board user guide on the ISL8277M product page. 6. for ? jc , the ?case temp? location is the center of the package underside. electrical specifications v in = v dd = 12v, f sw = 533khz, c out = 1340f, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit input and supply characteristics input supply current for controller i dd v in = v dd = 12v, v out = 0v, module not enabled 40 50 ma 6v internal reference supply voltage v r6 5.5 6.1 6.6 v internal regulator output voltage vdrvout v cc connected to vr 55 5.2 v 5v internal reference supply voltage v r5 i vr5 < 5ma 4.5 5.2 5.5 v 2.5v internal reference supply voltage v 25 2.25 2.50 2.75 v 5.5v internal reference supply voltage v r55 v dd > 6v; 0 - 80ma 5.7 v input supply voltage for controller readback resolution v dd_read_res 10 bits input supply voltage for controller readback total error ( note 10 ) v dd_read_err pmbus read 2 %fs output characteristics output voltage adjustment range v out_range v in > v out + 1.8v 0.54 5.50 v output voltage set-point range v out_res configured using pmbus 0.025 % output voltage set-point accuracy ( notes 8 , 10 ) v out_accy includes line, load, and temperature (-20c ta +85c) -1 +1 %v out output voltage readback resolution v out_read_res 10 bits ISL8277M fn8923 rev.1.00 page 8 of 57 aug 17, 2017 output voltage readback total error ( note 10 ) v out_read_err pmbus read -2 +2 %v out output current readback resolution i out_read_res 10 bits output current range ( note 9 )i out_range 25 a output current readback total error i out_read_err pmbus read at max load 2 a soft-start and sequencing delay time from enable to v out rise t on_delay configured using pmbus 2 5000 ms t on_delay accuracy t on_delay_accy 2 ms output voltage ramp-up time t on_rise configured using pmbus 0.5 100.0 ms output voltage ramp-up time accuracy t on_rise_accy 250 s delay time from disable to v out fall t off_delay configured using pmbus 2 5000 ms t off_delay accuracy t off_delay_accy 2 ms output voltage fall time t off_fall configured using pmbus 0.5 100.0 ms output voltage fall time accuracy t on_fall_accy 250 s power-good power-good delay v pg_delay configured using pmbus 0 5000 ms temperature sense temperature sense range t sense_range configurable via pmbus -50 150 ? c internal temperature se nsor accuracy int_temp accy tested at +100c -5 +5 ? c fault protection v dd undervoltage threshold range v dd_uvlo_range measured internally 4.18 16 v v dd undervoltage threshold accuracy ( note 10 ) v dd_uvlo_accy 2 %fs v dd undervoltage response time v dd_uvlo_delay 10 s v out overvoltage threshold range v out_ov_range factory default v out + 15 % configured using pmbus v out + 5 v out_max % v out undervoltage threshold range v out_uv_range factory default v out - 15 % configured using pmbus 0v out - 5 % v out ov/uv threshold accuracy ( note 8 ) v out_ov/uv_accy -2 +2 % v out ov/uv response time v out_ov/uv_delay 10 s output current limit set-point accuracy ( note 10 ) i limit_accy tested at i out _oc_fault_limit = 30a 10 %fs output current fault response time ( note 11 ) i limit_delay factory default 5 t sw over-temperature protection threshold (controller junction temperature) t junction factory default 125 ? c configured using pmbus -40 125 ? c thermal protection hysteresis t junction_hys 15 ? c electrical specifications v in = v dd = 12v, f sw = 533khz, c out = 1340f, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit ISL8277M fn8923 rev.1.00 page 9 of 57 aug 17, 2017 oscillator and switching characteristics switching frequency range f sw_range 296 1067 khz switching frequency set-point accuracy f sw_accy -5 +5 % minimum pulse width required from external sync clock ext_sync pw measured at 50% amplitude 150 ns drift tolerance for external sync clock ext_sync drift external sync clock equal to 500khz is not supported -10 +10 % logic input/output characteristics bias current at the logic input pins i logic_bias ddc, en, mgn, pg, sa, scl, sda, salrt, sync, uvlo, v mon , v set -100 +100 na logic input low threshold voltage v logic_in_low 0.8 v logic input high threshold voltage v logic_in_high 2.0 v logic output low threshold voltage v logic_out_low 2ma sinking 0.5 v logic output high threshold voltage v logic_out_high 2ma sourcing 2.25 v pmbus interface timing characteristic pmbus operating frequency f smb 100 400 khz notes: 7. compliance to datasheet limits is assu red by one or more methods: production test, characterization, and/or design. 8. v out measured at the termination of the v sen+ and v sen- sense points. 9. the max load current is determined by the thermal ? derating curves ? on page 12 . 10. ?fs? stand for full scale of recommended maximum operation range. 11. ?t sw ? stands for time period of operation switching frequency. electrical specifications v in = v dd = 12v, f sw = 533khz, c out = 1340f, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit ISL8277M fn8923 rev.1.00 page 10 of 57 aug 17, 2017 typical performance curves efficiency performance operating condition: t a = +25c, no air flow. c out = 1340f. typical values are used unless otherwise noted. figure 4. efficiency vs output current at v in = 5v, f sw = 533khz for various output voltages figure 5. efficiency vs switching frequency at v in = 5v, i out = 25a for various output voltages figure 6. efficiency vs output current at v in = 9v, f sw = 533khz for various output voltages figure 7. efficiency vs switching frequency at v in = 9v, i out = 25a for various output voltages figure 8. efficiency vs output current at v in = 12v, f sw = 533khz for various output voltages figure 9. efficiency vs switching frequency at v in = 12v, i out = 25a for various output voltages 60 65 70 75 80 85 90 95 100 1 3 5 7 9 11 13 15 17 19 21 23 25 i out (a) 0.8v 1v 1.2v 1.8v 2.5v 3.3v e f f i c i e n c y ( % ) 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 300 350 400 450 500 550 600 650 700 750 800 850 900 switching frequency (khz) 0.8v 1v 1.2v 1.5v 1.8v 2.5v 3.3v e f f i c i e n c y ( % ) e f f i c i e n c y ( % ) 60 65 70 75 80 85 90 95 100 1 3 5 7 9 11 13 15 17 19 21 23 25 i out (a) 0.8v 1v 1.2v 1.8v 2.5v 3.3v 5v e f f i c i e n c y ( % ) 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 300 350 400 450 500 550 600 650 700 750 800 850 900 switching frequency (kh z ) 0.8v 1v 1.2v 1.5v 1.8v 2.5v 3.3v 5v 60 65 70 75 80 85 90 95 100 1 3 5 7 9 1113151719212325 i out (a) 0.8v 1v 1.2v 1.8v 2.5v 3.3v 5v e f f i c i e n c y ( % ) e f f i c i e n c y ( % ) 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 300 350 400 450 500 550 600 650 700 750 800 850 900 switching frequency (khz) 0.8v 1v 1.2v 1.5v 1.8v 2.5v 3.3v 5v ISL8277M fn8923 rev.1.00 page 11 of 57 aug 17, 2017 transient response performance operating conditions: i out = 0/12.5a, i out slew rate > 20a/s, t a = +25c, olfm airflow. typical values are used unless otherwise noted. figure 10. 5v in to 1v out transient response, f sw =533khz, c out = 4x100f ceramic + 2x470f poscap figure 11. 5v in to 1.8v out transient response, f sw = 615khz, c out = 3x100f ceramic + 2x470f poscap figure 12. 12v in to 1v out transient response, f sw = 533khz, c out = 4x100f ceramic + 2x470f poscap figure 13. 12v in to 1.8v out transient response, f sw = 615khz, c out = 3x100f ceramic + 2x470f poscap figure 14. 12v in to 3.3v out transient response, f sw =615khz, c out = 3x100f ceramic + 2x470f poscap figure 15. 12v in to 5v out transient response, f sw = 727khz, c out = 3x100f ceramic + 2x470f poscap typical performance curves (continued) 50s/div ascr gain = 300 residual = 90 v out : 100mv/div i out : 5a/div 50s/div ascr gain = 350 residual = 90 i out : 5a/div v out : 100mv/div ascr gain = 300 residual = 90 v out : 100mv/div i out : 5a/div 50s/div 50s/div i out : 5a/div ascr gain = 300 residual = 90 v out : 100mv/div 50s/div ascr gain = 300 residual = 90 v out : 100mv/div i out : 5a/div 50s/div i out : 5a/div ascr gain = 350 residual = 90 v out : 100mv/div ISL8277M fn8923 rev.1.00 page 12 of 57 aug 17, 2017 derating curves all of the following curves were plotted at t j = +115c, f sw = 533khz figure 16. 5v in to 1v out figure 17. 12v in to 1v out figure 18. 5v in to 1.2v out figure 19. 12v in to 1.2v out figure 20. 5v in to 1.8v out figure 21. 12v in to 1.8v out typical performance curves (continued) 60 70 80 90 100 110 120 0 5 10 15 20 25 temperature (c) load current (a) 400 lfm 0 lfm 200 lfm 0 5 10 15 20 25 60 70 80 90 100 110 120 temperature (c) load current (a) 200 lfm 0 lfm 400 lfm 0 5 10 15 20 25 60 70 80 90 100 110 120 temperature (c) load current (a) 200 lfm 0 lfm 400 lfm 0 5 10 15 20 25 60 70 80 90 100 110 120 temperature (c) load current (a) 200 lfm 0 lfm 400 lfm 0 5 10 15 20 25 60 70 80 90 100 110 120 temperature (c) load current (a) 0 lfm 200 lfm 400 lfm 0 5 10 15 25 60 70 80 90 100 110 20 temperature (c) load current (a) 200 lfm 0 lfm 400 lfm ISL8277M fn8923 rev.1.00 page 13 of 57 aug 17, 2017 derating curves all of the following curves were plotted at t j = +115c, f sw = 533khz figure 22. 5v in to 2.5v out figure 23. 12v in to 2.5v out figure 24. 5v in to 3.3v out figure 25. 12v in to 3.3v out figure 26. 12v in to 5v out, 727khz typical performance curves (continued) 0 5 10 15 20 25 60 70 80 90 100 110 120 temperature (c) load current (a) 200 lfm 0 lfm 400 lfm 0 5 10 15 20 25 60 70 80 90 100 110 temperature (c) load current (a) 400 lfm 0 lfm 200 lfm 0 5 10 15 20 25 60 70 80 90 100 110 120 temperature (c) load current (a) 200 lfm 0 lfm 400 lfm 0 5 10 15 20 25 50 60 70 80 90 100 110 load current (a) temperature (c) 400 lfm 0 lfm 200 lfm 0 5 10 15 20 25 30 50 60 70 80 90 100 0 lfm 400 lfm 200 lfm load current (a) temperature (c) ISL8277M fn8923 rev.1.00 page 14 of 57 aug 17, 2017 typical application circuit figure 27. typical single-phase appl ication circuit for 1.2v/25a output ISL8277M vin vdd sgnd pgnd vout vsen+ vsen- sa vset salrt sda scl ddc pmbus interface vdrvin vdrvout c 1 c 2 + 2x22 220 c 3 10 r 1 2.2 c 5 c 4 10 1 c 7 c 8 + 4x100 2x470 (poscap) vr6 vr5 v25 vddc vswh phase pmbus address = 0x28 r 3 r 4 r 5 r 6 r 3 , r 4 , r 5 , r 6 = 4.7k en mgn ascr sync r 7 200 vaux 3.3v to 5v v in 4.5v to 13.2v v out 1.2v 25a ss/uvlo vout_command = 1.2v vcc vr55 10 c 6 notes: 12. r 4 and r 5 are not required if the pmbus host already has i 2 c pull-up resistors. 13. only one r 3 per ddc bus is required when ddc bus is shared with other modules. 14. r 7 is optional but recommended to sink possible ~100a back-flow current from the v sen+ pin. back-flow current is present only when the module is in a disabled state with power still available at the vdd pin. 15. unused pins (sync, ascr, mgn, ss/uvlo) can be no connect. 16. internal reference supply pins (v25, vddc, vr5, vr6) do no t need external capacitors and can be no connect. refer to ? pcb layout guidelines ? on page 21 for more information. note 15 note 16 note 14 note 12, 13 ISL8277M fn8923 rev.1.00 page 15 of 57 aug 17, 2017 table 2. ISL8277M design guide matrix and output voltage response v in (v) v out (v) c in (bulk) ( note 17 ) c in (ceramic) c out (bulk) c out (ceramic) ascr gain ( note 18 ) ascr residual ( note 18 )frequency v out deviation (mv) recovery time (us) step load (a) ( note 19 ) 5 0.8 2x150f 3x22f 2x470f 4x100f 160 90 364 80 25 12.5a 5 0.8 2x150f 3x22f 2x470f 4x100f 300 90 533 60 15 12.5a 5 0.9 2x150f 3x22f 2x470f 4x100f 160 90 364 80 25 12.5a 5 1 2x150f 3x22f 2x470f 4x100f 160 90 364 80 25 12.5a 5 1 2x150f 3x22f 2x470f 4x100f 300 90 533 60 18 12.5a 5 1.05 2x150f 3x22f 2x470f 4x100f 200 90 421 76 25 12.5a 5 1.1 2x150f 3x22f 2x470f 4x100f 250 90 471 72 20 12.5a 5 1.2 2x150f 3x22f 2x470f 4x100f 250 90 533 60 15 12.5a 5 1.3 2x150f 3x22f 2x470f 4x100f 300 90 533 58 20 12.5a 5 1.5 2x150f 3x22f 2x470f 4x100f 350 90 533 58 20 12.5a 5 1.8 2x150f 3x22f 2x470f 3x100f 350 90 615 62 30 12.5a 5 2.5 2x150f 3x22f 2x470f 3x100f 350 90 615 64 25 12.5a 5 3.3 2x150f 3x22f 2x470f 3x100f 300 90 615 70 35 12.5a 5 1.8 2x150f 3x22f 1x470f 3x100f 200 90 615 100 30 12.5a 5 2.5 2x150f 3x22f 1x470f 3x100f 200 90 615 100 35 12.5a 5 3.3 2x150f 3x22f 1x470f 3x100f 200 90 615 100 40 12.5a 12 0.8 2x150f 3x22f 2x470f 4x100f 160 90 364 80 18 12.5a 12 0.8 2x150f 3x22f 2x470f 4x100f 300 90 533 60 15 12.5a 12 0.9 2x150f 3x22f 2x470f 4x100f 160 90 364 80 18 12.5a 12 1 2x150f 3x22f 2x470f 4x100f 160 90 364 80 20 12.5a 12 1 2x150f 3x22f 2x470f 4x100f 300 90 533 60 12 12.5a 12 1.05 2x150f 3x22f 2x470f 4x100f 200 90 421 80 15 12.5a 12 1.1 2x150f 3x22f 2x470f 4x100f 200 90 471 78 15 12.5a 12 1.2 2x150f 3x22f 2x470f 4x100f 250 90 533 75 15 12.5a 12 1.3 2x150f 3x22f 2x470f 4x100f 300 90 533 72 12 12.5a 12 1.5 2x150f 3x22f 2x470f 4x100f 300 90 533 75 12 12.5a 12 1.8 2x150f 3x22f 2x470f 3x100f 300 90 615 78 10 12.5a 12 2.5 2x150f 3x22f 2x470f 3x100f 300 90 615 80 10 12.5a 12 3.3 2x150f 3x22f 2x470f 3x100f 300 90 615 82 10 12.5a 12 5 2x150f 3x22f 2x470f 3x100f 350 90 727 95 10 12.5a 12 1.8 2x150f 3x22f 1x470f 3x100f 200 90 615 102 12 12.5a 12 2.5 2x150f 3x22f 1x470f 3x100f 200 90 615 110 12 12.5a 12 3.3 2x150f 3x22f 1x470f 3x100f 200 90 615 118 12 12.5a 12 5 2x150f 3x22f 1x470f 3x100f 250 90 727 120 12 12.5a notes: 17. c in bulk capacitor is optional only for energy buffer from the long input power supply cable. 18. ascr gain and residual are selected to ensure that the phase margin is higher than 60 and gain margin is higher than 6db at -40c, +25c, +85c, and full load (25a). 19. output voltage response is tested with load step slew rate higher than 20a/s. ISL8277M fn8923 rev.1.00 page 16 of 57 aug 17, 2017 table 3. recommended i/o capacitor in table 2 vendors value part number murata, input ceramic 47f, 16v, 1210 grm32er61c476me15l murata, input ceramic 22f, 16 v, 1210 grm32er61e226ke15l taiyo yuden, input ceramic 47f, 16v, 1210 emk325bj476mm-t taiyo yuden, input ceramic 22f, 25v, 1210 tmk325bj226mm-t murata, output ceramic 100f, 6.3v, 1210 grm32er60j107m tdk, output ceramic 100f, 6.3v, 1210 c3225x5r0j107m avx, output ceramic 100f, 6.3v, 1210 12106d107mat2a sanyo poscap, input bulk 150f, 16v 16tqc150myf sanyo poscap, output bulk 470f, 4v 4tpe470mcl sanyo poscap, output bulk 470f, 6.3v 6tpf470mah ISL8277M fn8923 rev.1.00 page 17 of 57 aug 17, 2017 functional description smbus communications the ISL8277M provides an smbus digital interface that enables the user to configure all aspects of the module operation as well as monitor the input and output parameters. the ISL8277M can be used with any smbus host device. in addition, the module is compatible with pmbus power system management protocol specification parts i & ii version 1.2. the ISL8277M accepts most standard pmbus commands. when controlling the device with pmbus commands, it is recommended that the enable pin be tied to sgnd. the smbus device address is the only parameter that must be set by external pins. all other device parameters can be set with pmbus commands. output voltage selection the output voltage may be set to a voltage between 0.6v and 5v provided that the input voltage is higher than the desired output voltage by an amount sufficient to maintain regulation. the vset pin is used to set the output voltage to levels as shown in table 4 . the r set resistor is placed between the vset pin and sgnd. a standard 1% resistor is recommend. the output voltage may also be set to any value between 0.6v and 5v using a pmbus command vout_command. by default, v out_max is set 110% higher than v out set by the pin-strap resistor, which can be changed to any value up to 5.5v with pmbus command vout_max. soft-start delay and ramp times the ISL8277M follows an internal start-up procedure after power is applied to the vdd pin. the module requires approximately 60ms to 70ms to check for specific values stored in its internal memory and programmed by pin- strap resistors. once this process is completed, the device is ready to accept commands via the pmbus interface and the module is ready to be enabled. if the module is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the en pin. it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall in-rush current management strategy or to precisely control how fast a load ic is turned on. the ISL8277M gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay and ramp times can be programmed to custom values with pmbus commands ton_delay and ton_rise. when the delay time is set to 0ms, the device begins its ramp-up after the internal circuitry has initialized (approximately 2ms). when the soft -start ramp period is set to 0ms, the output ramps up as quickly as the output load capacitance and loop settings allow. it is generally recommended to set the soft-start ramp to a value greater than 500s to prevent inadvertent fault conditions due to excessive in-rush current. similar to the soft-start delay and ramp-up time, the delay and ramp-down time for soft-stop/off can be programmed with the pmbus commands toff_delay and toff_fall. in addition, the module can be configured as ?immediate off? with the command table 4. output voltage resistor settings v out (v) r set (k ) 0.60 10 0.65 11 0.70 12.1 0.75 13.3 0.80 14.7 0.85 16.2 0.90 17.8 0.95 19.6 1.00 21.5, or connect to sgnd 1.05 23.7 1.10 26.1 1.15 28.7 1.20 31.6, or open 1.25 34.8 1.30 38.3 1.40 42.2 1.50 46.4 1.60 51.1 1.70 56.2 1.80 61.9 1.90 68.1 2.00 75 2.10 82.5 2.20 90.9 2.30 100 2.50 110, or connect to v25 2.80 121 3.00 133 3.30 147 4.00 162 5.00 178 table 4. output voltage resistor settings (continued) v out (v) r set (k ) ISL8277M fn8923 rev.1.00 page 18 of 57 aug 17, 2017 on_off_config, such that the in ternal mosfets are turned off immediately after the delay time expires. the ss/uvlo pin can be used to program the soft- start/stop delay time and ramp time to some typical values as shown in table 5 . power-good the ISL8277M provides a power-good (pg) signal that indicates the output voltage is within a sp ecified tolerance of its target level and no fault condition exists. by default, the pg pin asserts if the output is within 10% of the target voltage. these limits and the polarity of the pin may be changed with pmbus command power_good_on. a pg delay period is defined as the time from when all conditions within the ISL8277M for asserting pg are met to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. a pg delay can be programmed with pmbus command power_good_delay. switching frequency and pll the device?s switching frequency is set from 296khz to 1067khz using the pin-strap method as shown in table 6 , or by using a pmbus command frequency_switch. the ISL8277M incorporates an internal phase- locked loop (pll) to clock the internal circuitry. the pll can be dr iven by an external clock source connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a cl ock source that is an external sync to other modules. refer to ? sync_config (e9h) ? on page 47 for more information. loop compensation the module loop response is programmable via the pmbus command ascr_config or by using the pin-strap method (ascr pin) according to table 7 . the ISL8277M uses the chargemode control algorithm that responds to output current changes within a single pwm switching cycle, achieving a smaller total output voltage variation with less output capacitance than traditional pwm controllers. table 5. soft-start/stop resistor settings delay time (ms) ramp time (ms) r set (k ) 5 2 12.1, 26.1, 56.2, or connect to sgnd 10 2 16.2, 34.8, 75 5 5 13.3, 28.7, 61.9, or open 10 5 17.8, 38.3, 82.5 20 5 21.5, 46.4, 100 5 10 14.7, 31.6, 68.1 10 10 19.6, 42.2, 90.9, or connect to v25 20 10 23.7, 51.1, 110 table 6. switching frequency resistor settings f sw (v) r set (k ) 296 14.7 or connect to sgnd 320 16.2 364 17.8 400 19.6 421 21.5 471 23.7 533 26.1 or open 571 28.7 615 31.6 727 34.8 800 38.3 842 42.2 889 46.4 1067 51.1 or connect to v25 table 7. ascr resistor settings ascr gain ascr residual r set (k ) 120 90 10 160 90 11, or connect to sgnd 200 90 12.1 250 90 13.3, or open 300 90 14.7 350 90 16.2 400 90 17.8 500 90 19.6 600 90 21.5 120 80 23.7 160 80 26.1 200 80 28.7 250 80 31.6 300 80 34.8 350 80 38.3 400 80 42.2 80 70 46.4 120 70 51.1 160 70 56.2 200 70 61.9 table 6. switching frequency re sistor settings (continued) f sw (v) r set (k ) ISL8277M fn8923 rev.1.00 page 19 of 57 aug 17, 2017 input undervoltage lockout (uvlo) the input undervoltage lockout (uvlo) prevents the ISL8277M from operating when the input fa lls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 4.18v and 16v using the pin-strap method as shown in table 8 , or by using a pmbus command vin_uv_fault_limit. fault response to an input undervoltage fault can be programmed with pmbus command vin_uv_fault_response. smbus module address selection each module must have its own unique serial address to distinguish between other devices on the bus. the module address is set by connecting a resistor between the sa pin and sgnd. table 9 lists the available module addresses. 250 70 68.1 300 70 75 120 100 82.5 160 100 90.9 200 100 100 250 100 110, or connect to v25 300 100 121 350 100 133 400 100 147 500 100 162 600 100 178 table 8. uvlo resistor settings uvlo (v) r uvlo (k ) 4.5 12.1, 13.3, 14.7, 16.2, 17.8, 19.6, 21.5, 23.7, open, connect to v25 and sgnd 4.3 26.1 4.59 28.7 5.06 31.6 5.57 34.8 6.13 38.3 6.75 42.2 7.42 46.4 8.18 51.1 10.8 56.2 10.8 61.9 10.8 68.1 10.8 75 10.8 82.5 10.8 90.9 10.8 100 table 7. ascr resistor settings (continued) table 9. smbus addre ss resistor selection r sa (k ) smbus address 10 19h 11 1ah 12.1 1bh 13.3 1ch 14.7 1dh 16.2 1eh 17.8 1fh 19.6 20h 21.5 21h 23.7 22h 26.1 23h 28.7 24h 31.6 25h 34.8 or connect to sgnd 26h 38.3 27h 42.2 or open 28h 46.4 29h 51.1 2ah 56.2 2bh 61.9 2ch 68.1 2dh 75 2eh 82.5 2fh 90.9 30h 100 31h ISL8277M fn8923 rev.1.00 page 20 of 57 aug 17, 2017 output overvoltage protection the ISL8277M offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator is used to compare the actual output voltage (seen at the v sen+ and v sen- pins) to a threshold set to 15% higher than the target output voltage (the default setting). fault threshold can be programmed to a desired level with pmbus command vout_ov_fault_limit. if the v sen+ voltage exceeds this threshold, the module will initiate an immediate shutdown without retry. retry settings can be programmed with pmbus command vout_ov_fault_response. internal to the module, two 100 resistors are populated from vout to vsen+ and sgnd to vsen to protect the device from overvoltage conditions in case of an open at vsense pins and differential remote sense traces due to assembly error. as long as differential remote sense traces have low resistance, v out regulation accuracy is not sacrificed. output prebias protection an output prebias condition exis ts when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. certain applications require that the converter not be allowed to si nk current during start-up if a prebias condition exists at the output. the ISL8277M provides prebias protection by sampling the output voltage prior to initiating an output ramp. if a prebias voltage lower than the target voltage exists after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage, and both drivers are enabled. the output voltage is then ramped to the final regulation value at the preconfigured ramp rate. the actual time the output takes to ramp from the prebias voltage to the target voltage varies, depending on the prebias voltage, however, the total time elapsed from when the delay period expires and when the output reaches its target value will match the preconfigured ramp time (see figure 28 ). if a prebias voltage is higher than the target voltage after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage, and both drivers are enabled with a pwm duty cycle that would ideally create the prebias voltage. once the preconfigured soft-start ramp period has expired, the pg pin is asserted (assuming the prebias voltage is not higher than the overvoltage limit). the pwm then adjusts its duty cycle to match the original target voltage, and the output ramps down to the preconfigured output voltage. if a prebias voltage is higher than the overvoltage limit, the device does not initiate a turn-on sequence and declares an overvoltage fault condition. the device then responds based on the output overvoltage fault response setting programmed with pmbus command vout_ov_fault_response. output overcurrent protection the ISL8277M can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. average output overcurrent fault threshold can be programmed with pmbus comman d iout_oc_fault_limit. the module automatically programs the peak inductor current fault threshold by reading real-time inpu t voltage, switching frequency, and vout_command to calculate the inductor ripple current. when the peak inductor current crosses the peak inductor current fault threshold for five su ccessive cycle modules, it will initiate an immediate shutdown. the default response from an ov ercurrent fault is an immediate shutdown without retry. retry se ttings can be programmed with pmbus command mfr_iout _oc_fault_response. thermal overload protection the ISL8277M includes a therma l sensor that continuously measures the internal temperat ure of the module and shuts down the controller when the temperature exceeds the preset limit. the default temperature limit is set to +125c in the factory, but can be changed with pmbus command ot_fault_limit. the default response from an over-temperature fault is an immediate shutdown without retry. retry settings can be programmed with pmbus co mmand ot_fault_response. if the user has configured the module to retry, the controller waits the preset delay period and then checks the module temperature. if the temperature has dropped below a threshold that is approximately +15c lower than the selected temperature fault limit, the controller attempts to restart. if the figure 28. output responses to pre-bias voltages desired output voltage pre-bias voltage v out time ton- delay ton- rise desired output voltage pre-bias voltage v out time v prebias < v target v prebias > v target ton- rise ton- delay ISL8277M fn8923 rev.1.00 page 21 of 57 aug 17, 2017 temperature still exceeds the faul t limit, the controller waits the preset delay period and retries the temperature. digital-dc bus the digital-dc communications (ddc) bus is used to communicate between intersil digital power modules and digital controllers. this dedicated bu s provides the communication channel between devices for feat ures such as sequencing and fault spreading. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bus to ensure the rise time as shown in equation 1 : where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to an external 3.3v or 5v supply as long as this voltage is present before or during device power-up. in principle, each device connected to the ddc bus presents approximately 10pf of capacitive loading, and each inch of fr4 pcb trace introduces approximately 2pf. the ideal design uses a central pull-up resistor that is well-matched to the total load capacitance. phase spreading when multiple point-of-load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device, such that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. because the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced, and the power losses proportional to the i rms 2 are reduced dramatically. to enable phase spreading, all converters must be synchronized to the same switching clock. the phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments with pmbus command interleave. output sequencing a group of digital-dc modules or devices may be configured to power-up in a predetermined sequence. this feature is especially useful for preventing latch-up when powering advanced processors (fpgas and asics that require one supply to reach its operating voltage) prior to anot her supply reaching its operating voltage. multi-device sequencing can be achieved by configuring each device with pmbus command sequence. multiple device sequencing is configured by i ssuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that follows in the sequencing chain. the enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven lo w to initiate a sequenced turnoff of the group. fault spreading digital dc modules and devices can be configured to broadcast a fault event over the ddc bus to the other devices in the group with pmbus command ddc_group. when a non-destructive fault occurs and the device is conf igured to shutdown on a fault, the device shuts down and broadcasts the fault event over the ddc bus. the other devices on the ddc bus shutdown simultaneously, if configured to do so, and attempt to restart in their prescribed order. monitoring via smbus a system controller can monitor a wide variety of different ISL8277M system parameters with pmbus commands: ?read_vin ?read_vout ?read_iout ? read_internal_temp ? read_external_temp ? read_duty_cycle ? read_freqeuncy ?mfr_read_vmon snapshot parameter capture the ISL8277M offers a special feature to capture parametric data and some fault status following a fault. a detailed description is provided in ? snapshot (eah) ? on page 48 . nonvolatile memory the ISL8277M has internal nonvolatile memory that stores user configurations. integrated securi ty measures ensure that users can only restore the module to a level that has been made available to them. during the initialization process, the ISL8277M checks for stored values contained in its internal nonvolatile memory. modules are shipped with factor y default configurations. most settings can be overwritten with pmbus commands and can be stored in nonvolatile memory with the pmbus command store_user_all. pcb layout guidelines to achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary. ?for v dd > 6v, the recommended pcb layout is shown in figure 29 . leave v25, v ddc , vr5, and vr6 as ?no connect (nc)?. ? for 5.5v ? v dd ? 6v, connect vddc pin to vr6 pin. for 4.5 ? v dd < 5.5v, connect vddc pin to vr6 and vr5 pin. an rc filter is required at the input of vdrvin pin if input supply is shared with the vin pin. ? establish a separate sgnd plane and pgnd plane, then connect the sgnd to the pgnd plane as shown in figure 30 in the middle layer. for making connections between sgnd/pgnd on the top layer and other layers, use multiple rise time r pu ? c load 1 ? s ? = (eq. 1) ISL8277M fn8923 rev.1.00 page 22 of 57 aug 17, 2017 vias for each pin to connect to the inner sgnd/pgnd layer. do not connect sgnd directly to pgnd on a top layer. connecting sgnd directly to pgnd without establishing an sgnd plane will bypass the decoupling capacitor at internal reference supplies, making the controller susceptible to noise. ? place ceramic capacitors between vin and pgnd, vout and pgnd, and the bypass capacitors between vdd and the ground plane, as close to the module as possible to minimize high frequency noise. ? use large copper areas for power path (vin, pgnd, vout) to minimize conduction loss an d thermal stress. also, use multiple vias to connect the po wer planes in different layers. extra ceramic capacitors at vin and vout can be placed on the bottom layer under vin and vout pads when multiple vias are used for connecting copper pads on top and bottom layers. ? connect differential remote-sensing traces to the regulation point to achieve a tight output voltag e regulation. route a trace from and v sen+ to the point-of-load where the tight output voltage is desired. avoid routing any sensitive signal traces, such as the vsense signal near vswh pads. ? for noise sensitive applications , it is recommended that the user connect the vswh pads only on the top layer; however, thermal performance will be sacrificed. external airflow might be required to keep module heat at desired level. for applications where switching nois e is less critical, an excellent thermal performance can be achieved in the ISL8277M module by increasing copper mass attached to vswh pad. to increase copper mass on the vswh node, create copper islands in the middle and bottom layers under the vswh pad and connect them to the top layer with multiple vias. make sure to shield those copper islands with a pgnd layer to avoid any interference to noise sensitive signals. thermal considerations experimental power loss curves, along with ja from thermal modeling analysis, can be us ed to evaluate the thermal consideration for the module. the derating curves are derived from the maximum power allowed while maintaining the temperature below the maximum junction temperature of +125c. in actual application, other heat sources and design margins should be considered. package description the structure of the ISL8277M belongs to the high density array (hda) no-lead package. this ki nd of package has advantages, such as good thermal and electric al conductivity, low weight, and small size. the hda package is applicable for surface mounting technology and is being more re adily used in the industry. the ISL8277M contains several types of devices, including resistors, capacitors, inductors, and control ics. the ISL8277M is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper lead frame and multi-component assembly is over-molded with polymer mold compound to protect these devices. the package outline, a typical pcb land pattern design, and a typical stencil opening edge position are shown in the ? package outline drawing ? section starting on page 51 . the module has a small size of 17mmx19mmx3.6mm. figure 31 shows typical reflow profile parameters. these guidelines are general design rules. users can modify parameters according to their application. figure 29. recommended layout - top pcb layer en sync scl sda salrt sa mgn vset nc sgnd ascr vsen - nc nc vsen+ nc a b c sgnd vdd vout sgnd vswh pgnd vin pgnd pg uvlo pgnd phase nc nc vddc vr25 vr5 vr6 pgnd nc c vin c vdd sgnd pgnd ddc v drvout v drvin c c vout vr55 vcc r c c figure 30. recommended layout - connect sgnd to pgnd in the middle pcb layer after establishing separate sgnd and pgnd pgnd connect sgnd to pgnd in the middle layer sgnd sgnd sgnd sgnd pgnd pgnd pgnd ISL8277M fn8923 rev.1.00 page 23 of 57 aug 17, 2017 pcb layout pattern design the bottom of the ISL8277M is a lead-frame footprint, which is attached to the pcb by surface mounting process. the pcb land pattern is shown in the ? package outline drawing ? section starting on page 51 . the pcb layout pattern is an array of solder mask defined pcb lands which align with the perimeters of the hda exposed pads and i/o termination dimensions. the thermal lands on the pcb layout also feature an array of solder mask defined lands and should match 1:1 with the package exposed die pad perimeters. the exposed solder mask define d pcb land area should be 50-80% of the available module i/o area. thermal vias a grid of 1.0mm to 1.2mm pitch thermal vias, which drops down and connects to buried copper plane(s), should be placed under the thermal land. the vias should be about 0.3mm to 0.33mm in diameter with the barrel plated to about 1.0 ounce copper. although adding more vias (by de creasing via pitch) wi ll improve the thermal performance, diminishing returns will be seen as more and more vias are added. simply use as many vias as practical for the thermal land size and that your bo ard design rules will allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50m to 75m (2mil to 3m il) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joints. the stencil aperture size to sold er mask defined pcb land size ratio should typically be 1:1. the aperture width can be reduced slightly to help prevent solder bridging between adjacent i/o lands. a typical solder stencil pattern is shown in the ? package outline drawing ? section starting on page 51 . the user should consider the symmetry of the whole stencil pattern when designing its pads. a laser cut, stainless steel stencil with electropolished trapezoidal walls is recommended. electropolishing ?smooths? the aperture walls resulting in reduced surface friction and better paste release, which reduces voids. using a trapezoidal section aperture (tsa) also promotes paste release and forms a ?brick like? paste deposit that assists in firm component placement. a 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) hda. reflow parameters due to the low mount height of the hda, a ?no clean? type 3 solder paste per ansi/j-std-005 is recommended. nitrogen purge is also recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, thus it is not practical to define a specific soldering profile just for the hda. the profile given in figure 31 is provided as a guideline, to be customized for varying manufacturing practices and applications . * figure 31. typical reflow profile 0300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) duration (s) slow ramp (3c/s max) and soak from +150c to +200c for 60s~180s ramp rate ? 1.5c from +70c to +90c peak temperature ~+245c; typically 60s-150s above +217c keep less than 30s within 5c of peak temp. ISL8277M fn8923 rev.1.00 page 24 of 57 aug 17, 2017 pmbus command summary command code command name description type data format default value default setting page 01h operation sets enable, disable, and v out margin modes. r/w byte bit 28 02h on_off_config configures the en pin and pmbus commands to turn the unit on/off. r/w byte bit 17h hardware enable, immediate off 28 03h clear_faults clears fault indications. send byte 29 15h store_user_all stores all pmbus values written since last restore at user level. send byte 29 16h restore_user_all restores pmbus settings that were stored using store_user_all. send byte 29 20h vout_mode preset to defined data format of v out commands. read byte bit 13h linear mode, exponent = -13 29 21h vout_command sets the nominal value of the output voltage. r/w word l16u pin-strap 29 23h vout_cal_offset applies a fixed offset voltage to the vout_command. r/w word l16s 0000h 0v 30 24h vout_max sets the maximum possible value of v out . 110% of pin-strap v out . r/w word l16u 1.1 * v out pin-strap 30 25h vout_margin_high sets the value of the v out during a margin high. r/w word l16u 1.05 * v out pin-strap 30 26h vout_margin_low sets the value of the v out during a margin low. r/w word l16u 0.95 * v out pin-strap 30 27h vout_transition_rate sets th e transition rate during margin or other change of v out . r/w word l11 ba00h 1v/ms 30 28h vout_droop sets the loadline (v/i slope) resistance for the rail. r/w word l11 0000h 0mv/a 31 33h frequency_switch sets the switching frequency. r/w word l11 pin-strap 31 37h interleave configures a phase offset between devices sharing a sync clock. r/w word bit set based on pmbus address 31 38h iout_cal_gain sense resistance for inductor dcr current sensing. r/w word l11 b380h 0.875m 31 39h iout_cal_offset sets the current-sense offset. r/w word l11 0000h 0a 31 40h vout_ov_fault_limit sets the v out overvoltage fault threshold. r/w word l16u 1.15 * v out pin-strap 32 41h vout_ov_fault_response configures the v out overvoltage fault response. r/w byte bit 80h disable and no retry 32 42h vout_ov_warn_limit sets the v out overvoltage warn threshold. r/w word l16u 1.10 * v out pin-strap 32 43h vout_uv_warn_limit sets the v out undervoltage warn threshold. r/w word l16u 0.9 * v out pin-strap 32 44h vout_uv_fault_limit sets the v out undervoltage fault threshold. r/w word l16u 0.85 * v out pin-strap 32 45h vout_uv_fault_response configures the v out undervoltage fault response. r/w byte bit 80h disable and no retry 33 46h iout_oc_fault_limit sets the i out average overcurrent fault threshold. r/w word l11 dbc0h 30a 33 4bh iout_uc_fault_limit sets the i out average undercurrent fault threshold. r/w word l11 dc3fh -30a 33 4fh ot_fault_limit sets the over-temperature fault threshold. r/w word l11 ebe8h +125c 33 ISL8277M fn8923 rev.1.00 page 25 of 57 aug 17, 2017 50h ot_fault_response configures the over -temperature fault response. r/w byte bit 80h disable and no retry 33 51h ot_warn_limit sets the over-temperature warning limit. r/w word l11 eb70h +110c 34 52h ut_warn_limit sets the under-temperature warning limit. r/w word l11 dc40h -30c 34 53h ut_fault_limit sets the under-temperature fault threshold. r/w word l11 e530h -45c 34 54h ut_fault_response configures the under-temperature fault response. r/w byte bit 80h disable and no retry 34 55h vin_ov_fault_limit sets the v in overvoltage fault threshold. r/w word l11 d3a0h 14.5v 34 56h vin_ov_fault_response configures the v in overvoltage fault response. r/w byte bit 80h disable and no retry 35 57h vin_ov_warn_limit sets the input overvoltage warning limit. r/w word l11 d343h 13.05v 35 58h vin_uv_warn_limit sets the input undervoltage warning limit. r/w word l11 1.10*vin uv fault limit 35 59h vin_uv_fault_limit sets the v in undervoltage fault threshold. r/w word l11 pin-strap 35 5ah vin_uv_fault_response configures the v in undervoltage fault response. r/w byte bit 80h disable and no retry 36 5eh power_good_on sets the voltage threshold for power-good indication. r/w word l16u 0.9*vout pin-strap 36 60h ton_delay sets the delay time from enable to start of v out rise. r/w word l11 pin-strap 36 61h ton_rise sets the rise time of v out after enable and ton_delay. r/w word l11 pin-strap 36 64h toff_delay sets the delay time from disable to start of v out fall. r/w word l11 pin-strap 36 65h toff_fall sets the fall time for v out after disable and toff_delay. r/w word l11 pin-strap 37 78h status_byte returns an abbreviated status for fast reads. read byte bit 00h no faults 37 79h status_word returns information with a summary of the unit's fault condition. read word bit 0000h no faults 38 7ah status_vout returns the v out specific status. read byte bit 00h no faults 38 7bh status_iout returns the i out specific status. read byte bit 00h no faults 39 7ch status_input returns specific status specific to the input. read byte bit 00h no faults 39 7dh status_temp returns the temperature specific status. read byte bit 00h no faults 39 7eh status_cml returns the communication, logic, and memory specific status. read byte bit 00h no faults 40 80h status_mfr_specific returns the vmon and external sync clock specific status. read byte bit 00h no faults 40 88h read_vin returns the input voltage reading. read word l11 40 8bh read_vout returns the output voltage reading. read word l16u 40 pmbus command summary (continued) command code command name description type data format default value default setting page ISL8277M fn8923 rev.1.00 page 26 of 57 aug 17, 2017 8ch read_iout returns the output current reading. read word l11 41 8dh read_internal_temp returns the temperature reading internal to the device. read word l11 41 8eh read_external_temp returns the temperature reading from external monitor source. read word l11 41 94h read_duty_cycle returns the duty cycle reading during the enable state. read word l11 41 95h read_frequency returns the measured operating switch frequency. read word l11 41 99h mfr_id sets a user defined identification. r/w block ascii null 41 9ah mfr_model sets a user defined model. r/w block ascii null 42 9bh mfr_revision sets a user defined revision. r/w block ascii null 42 9ch mfr_location sets a user defined location identifier. r/w block ascii null 42 9dh mfr_date sets a user defined date. r/w block ascii null 42 9eh mfr_serial sets a user defined serialized identifier. r/w block ascii null 42 a8h legacy_fault_group broadcast faults when mixed with old generation modules r/w block bit 00000000h 43 b0h user_data_00 sets a user defined data. r/w block ascii null 43 d0h isense_config configures isense related features. r/w byte bit 05h 256ns blanking time, mid range 44 d1h user_config configures several user-level features. r/w byte bit 00h open-drain pg, xtemp disabled 44 d3h ddc_config configures the ddc bus. r/w byte bit 00h set based on pmbus address 45 d4h power_good_delay sets the delay between v out > pg threshold and asserting the pg pin. r/w word l11 ca00h 4ms 45 dfh ascr_config configures ascr control loop. r/w block cus pin-strap 45 e0h sequence identifies the rail ddc id to perform multi-rail sequencing. r/w word bit 0000h prequel and sequel disabled 46 e2h ddc_group sets rail ddc ids to obey faults and margining spreading information. r/w block bit 000000h broadcast disabled 46 e4h device_id returns the 16-byte (character) device identifier string. read block ascii reads device version 47 e5h mfr_iout_oc_fault_response configures the i out overcurrent fault response. r/w byte bit 80h disable and no retry 47 e6h mfr_iout_uc_fault_response configures the i out undercurrent fault response. r/w byte bit 80h disable and no retry 47 e9h sync_config configures the sync pin. r/w byte bit 00h 47 eah snapshot returns 32-byte read-back of parametric and status values. read block bit 48 ebh blank_params returns recently changed parameter values. read block bit ff?ffh 48 f3h snapshot_control snapshot feature control command. w byte bit 48 f4h restore_factory restores device to the factory default values. write block 49 pmbus command summary (continued) command code command name description type data format default value default setting page ISL8277M fn8923 rev.1.00 page 27 of 57 aug 17, 2017 pmbus data formats linear-11 (l11) l11 data format uses 5-bit two?s compliment exponent (n) and 11-b it two?s compliment mantissa (y) to represent real world decim al value (x). relation between real world decimal value (x), n and y is: x = y 2 n linear-16 unsigned (l16u) the l16u data format uses a fixed exponent (hard-coded to n = -1 3h) and a 16-bit unsigned intege r mantissa (y) to represent rea l world decimal value (x). relation between real world decimal value (x), n and y is: x = y 2 -13 linear-16 signed (l16s) the l16s data format uses a fixed exponent (hard-coded to n = - 13h) and a 16-bit two?s compliment mantissa (y) to represent rea l world decimal value (x). relation between real world decimal value (x), n, and y is: x = y 2 -13 bit field (bit) a break down of bit field is provided in pmbus on ? pmbus command descriptions ? on page 28 . custom (cus) a break down of custom data format is provided in pmbus ? pmbus command descriptions ? on page 28 . a combination of bit field and integer are common type of custom data format. ascii (asc) a variable length string of text charac ters that uses the ascii data format. f5h mfr_vmon_ov_fault_limit returns the vmon overvoltage threshold. read word l11 cb00h 6v 49 f6h mfr_vmon_uv_fault_limit returns the vmon undervoltage threshold. read word l11 ca00h 4v 49 f7h mfr_read_vmon returns the vmon voltage reading. vmon is used to monitor vdrvout (pin 8) voltage through an internal 16:1 resistor divider. read word l11 49 f8h vmon_ov_fault_response returns the vmon overvoltage response. read byte bit 80h disable and no retry 49 f9h vmon_ov_fault_response returns the vmon undervoltage response. read byte bit 80h disable and no retry 49 pmbus command summary (continued) command code command name description type data format default value default setting page data byte high data byte low exponent (n) mantissa (y) 76543210 76543210 ISL8277M fn8923 rev.1.00 page 28 of 57 aug 17, 2017 pmbus use guidelines the pmbus is a powerful tool that allows the user to optimize circuit performance by configuring devices for their application. when configuring a device in a circuit, the device should be disabl ed whenever most settings are ch anged with pmbus commands. some exceptions to this recommendation are operation, on_off_config, clear_faults, vout_command, vout_margin_high, vout_margin_low, and asccr_config. any command can be read whil e the device is enabled. many commands do not take effect until after the device has been re-enabled, hence the recommendati on that commands that change device settings are written whil e the device is disabled. when sending the store_default_all, store_user_all, rest ore_default_all, and restor e_user_all commands, it is recommended that no other commands ar e sent to the device for 100ms afte r sending store or restore commands. in addition, there should be a 2ms delay between repeated read commands sent to the same device. when sending any other command, a 5ms delay is recommended between re peated commands sent to the same device. summary all commands can be read at any time. always disable the device when writing comman ds that change device settings. exceptions to this rule are commands intended to b e written while the device is enabled, for example, vout_margin_high. to be sure a change to a device setting has taken effect, writ e the store_user_all command, then cycle input power and re-enabl e. pmbus command descriptions operation (01h) definition: sets enable, disable, and v out margin settings. data values of operation that force margin high or low only take effect when the mgn pin is left open (i.e ., in the nominal margin state). data length in bytes : 1 data forma t: bit type : r/w default value : units : n/a on_off_config (02h) definition: configures the interpretation and coordination of the operation command and the enable pin (en). data length in bytes : 1 data format : bit type : r/w default value : 17h (device starts from enable pin with immediate off) units : n/a settings actions 04h immediate off (no sequencing) 44h soft off (with sequencing) 84h on - nominal 94h on - margin low a4h on - margin high settings actions 00h device starts any time power is present regard less of enable pin or operation command states. 16h device starts from enable pin with soft off. 17h device starts from enab le pin with immediate off. 1ah device starts from operation command. ISL8277M fn8923 rev.1.00 page 29 of 57 aug 17, 2017 clear_faults (03h) definition : clears all fault bits in all registers and releases the salr t pin (if asserted) simultaneously. if a fault condition still ex ists, the bit will reassert immediately. this command will not restart a device if it has shut down, it will only clear the faults. data length in bytes : 0 byte data format : n/a type : send only default valu e: n/a units : n/a reference: n/a store_user_all (15h) definition : stores all pmbus settings from the operating memory to the nonvolatile user store memory. to clear the user store, perform a restore_factory then store_user_all. to add to the user store, perform a restore_user_all, write commands to be added, then store_user_all. this command can be used during device operation, but the device will be unresponsive for 20ms while storing values. data length in bytes : 0 data format : n/a type : send only default value : n/a units: n/a restore_user_all (16h) definition: restores all pmbus settings from the user store memory to the operating memory. command performed at power-up. security level is changed to level 1 following this command. this command can be used during device operation, but the device w ill be unresponsive for 20ms while storing values. data length in bytes: 0 data format: n/a type: send only default value: n/a units: n/a vout_mode (20h) definition: reports the v out mode and provides the exponent used in calculating several v out settings. fixed with linear mode with default exponent (n) = -13 data length in bytes: 1 data format: bit type: read only default value: 13h (linear mode, n = -13) units: n/a vout_command (21h) definition: sets or reports the target output voltag e. this command cannot set a value higher than either vout_max or 110% of the pin- strap v out setting. data length in bytes: 2 data format: l16u type: r/w default value: pin-strap setting units: volts range: 0v to vout_max ISL8277M fn8923 rev.1.00 page 30 of 57 aug 17, 2017 vout_cal_offset (23h) definition: applies a fixed offset voltage to the output voltage command value. this command is typically used by the user to calibrate a device in the application circuit. data length in bytes: 2 data format: l16s type: r/w default value: 0000h units: volts vout_max (24h) definition: sets an upper limit on the output voltage the unit can co mmand regardless of any other commands or combinations. the intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructi ve level rather than to be the primary output overprot ection. default value can be changed via pmbus. data length in bytes: 2 data format: l16u type: r/w default value: 1.10xvout_command pin--strap setting units: volts range: 0v to 6v vout_margin_high (25h) definition: sets the value of the v out during a margin high. this vout_margin_high command loads the unit with the voltage to which the output is to be changed when the operation command is set to ?margin high?. data length in bytes: 2 data format: l16u type: r/w word default value: 1.05 x vout_command pin-strap setting units: v range: 0v to vout_max vout_margin_low (26h) definition: sets the value of the v out during a margin low. this vout_margin_low comm and loads the unit with the voltage to which the output is to be changed when the op eration command is set to ?margin low?. data length in bytes: 2 data format: l16u type: r/w default value: 0.95 x vout_command pin-strap setting units: v range: 0v to vout_max vout_transition_rate (27h) definition: sets the rate at which the output should change voltage when the device receives an operation command (margin high, margin low) that causes the output voltage to change. the maxi mum possible positive value of the two data bytes indicates that the device should make the transi tion as quickly as possible. data length in bytes: 2 data format: l11 type: r/w default value: ba00h (1.0 v/ms) units : v/ms range: 0.1 to 4v/ms ISL8277M fn8923 rev.1.00 page 31 of 57 aug 17, 2017 vout_droop (28h) definition: sets the effective load line (v/i slope) for the rail in which the device is used. it is the rate, in mv/a, at which the outpu t voltage decreases (or increa ses) with increasing (or decreasi ng) output current for use with ad aptive voltage positioning schem es. data length in bytes: 2 data format: l11 type: r/w default value: 0000h (0mv/a) units: mv/a range: 0 to 40mv/a frequency_switch (33h) definition: sets the switching frequency of the device . initial default value is defined by a pin-strap and this value can be overridden by writing this command via pmbus. if an external sync is utilized, this value should be set as close as possible to the external clock value. the output must be disabled when writing this command. data length in bytes: 2 data format: l11 type: r/w default value: pin-strap setting units: khz range: 300khz to 1066mhz interleave (37h) definition: configures the phase offset of a device th at is sharing a common sync clock with ot her devices. a value of 0 for the number in group field is interpreted as 16 to allow fo r phase spreading groups of up to 16 devices. data length in bytes: 2 data format: bit type: r/w default value: pin-strap setting units: khz iout_cal_gain (38h) definition: sets the effective impedance across the current sense ci rcuit for use in calculating output current at +25c. data length in bytes: 2 data format: l11 type : r/w default value: b380h (0.875m ) units: m iout_cal_offset (39h) definition: used to null out any offsets in the output current-sensing ci rcuit, and to compensate for delayed measurements of current ramp due to isense blanking time. data length in bytes: 2 data format: l11 type : r/w default value: 0000h (0a) units: a bits purpose value description 15:2 reserved 0 reserved 11:8 group number 0 to 15 sets a number to a group of interleaved rails 7:4 number in group 0 to 15 sets the number of rails in the group a value of 0 is interpreted as 16 3:0 position in group 0 to 15 sets position of the device's rail within the group ISL8277M fn8923 rev.1.00 page 32 of 57 aug 17, 2017 vout_ov_fault_limit (40h) definition: sets the v out overvoltage fault threshold. data length in bytes: 2 data format: l16u type: r/w default value: 1.15xvout_command pin-strap setting units: v range: 0v to vout_max vout_ov_fault_response (41h) definition: configures the v out overvoltage fault response. note that the devi ce cannot be set to ignore this fault mode. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a vout_ov_warning_limit (42h) definition: sets the v out overvoltage wring threshold. power-good signal is pull ed low when output voltag e goes higher than this threshold. data length in bytes : 2 data format: l16u type: r/w default value: 1.1xvout_command pin-strap setting units: v range: 0v to vout_max vout_uv_warning_limit (43h) definition: sets the v out undervoltage warning threshold. power-good signal is pulled low when output voltage goes lower than this threshold. data length in bytes: 2 data format: l16u type: r/w default value: 0.9xvout_command pin-strap setting units: v range: 0v to vout_max vout_uv_fault_limit (44h) definition: sets the v out undervoltage fault threshold. this fault is masked during ramp or when disabled. data length in bytes: 2 data format: l16u type: r/w default value: 0.85xvout_command pin-strap setting units: v range: 0v to vout_max settings actions 80h disable with no retry bfh disable and continuous retry with 70ms delay ISL8277M fn8923 rev.1.00 page 33 of 57 aug 17, 2017 vout_uv_fault_response (45h) definition: configures the v out undervoltage fault response. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable, no retry) units: n/a iout_oc_fault_limit (46h) definition: sets the i out average overcurrent fault threshold. device will automa tically calculate peak inductor overcurrent fault limit. data length in bytes: 2 data format: l11 type: r/w default value: dbc0h 30a units: a range: -100 to 100a iout_uc_fault_limit (4bh) definition: sets the i out average undercurrent fault threshold. de vice will automatically calculate valle y inductor undercurrent fault limit. data length in bytes: 2 data format: l11 type: r/w default value: dc3fh -30a units: a range: -100 to 100a ot_fault_limit (4fh) definition: sets the temperature at which the device should indicate an over-temperature fault. note that the temperature must drop below ot_warn_limit to clear this fault. data length in bytes: 2 data format: l11 type: r/w default value: ebe8h (+125 ? c) units: celsius range: 0 c to +175 c ot_fault_response (50h) definition: instructs the device on what action to take in response to an over-temperature fault. data length in bytes: 1 data format: bit type : r/w fault value: 80h (disable and no retry) units: n/a settings actions 80h disable with no retry bfh disable and continuous retry with 70ms delay settings actions 80h disable with no retry bfh disable and continuous retry with 70ms delay ISL8277M fn8923 rev.1.00 page 34 of 57 aug 17, 2017 ot_warn_limit (51h) definition: sets the temperature at which the device should indicate an over-temperature warning alarm. in response to the ot_warn_limit being exceeded, the device: sets the temper ature bit in status_word, sets the ot_warning bit in status_temperature, and notifies the host. data length in bytes: 2 data format: l11 type : r/w default value: eb70h (+110c) units: celsius range : 0c to +175c ut_warn_limit (52h) definition: sets the temperature at which the device should indicate an under-temperature warning alarm. in response to the ut_warn_limit being exceeded, the device: sets the temperature bit in status_word, sets the ut_warning bit in status_temperature, and notifies the host. data length in bytes: 2 data format: l11 type : r/w default value: dc40h (-30c) units: celsius range : -55c to +25c ut_fault_limit (53h) definition: sets the temperature, in degrees celsius, of the unit where it should indicate an under-temperature fault. note that the temperature must rise above ut_w arn_limit to clear this fault. data length in bytes: 2 data format: l11 type: r/w default value: e530h (-45c) units: celsius range: -55c to +25c ut_fault_response (54h) definition: configures the under-temperature fault response as defined by the following table. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable, no retry) units: n/a vin_ov_fault_limit (55h) definition: sets the v in overvoltage fault threshold. data length in bytes: 2 data format: l11 type: r/w default value: d3a0h (14.5v) units: v range: 0v to 16v settings actions 80h disable with no retry bfh disable and continuous retry with 70ms delay ISL8277M fn8923 rev.1.00 page 35 of 57 aug 17, 2017 vin_ov_fault_response (56h) definition: configures the v in overvoltage fault response as defined by the followin g table. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a vin_ov_warn_limit (57h) definition: sets the v in overvoltage warning threshold as defined by the ta ble below. in response to the ov_warn_limit being exceeded, the device: sets the none of the above and input bits in status_word, sets the vin_ov_warning bit in status_input, and notifies the host. data length in bytes: 2 data format: l11 type : r/w protectable: yes default value: d343h (13.05v) units: v range : 0v to 16v vin_uv_warn_limit (58h) definition: sets the v in undervoltage warning threshold. if a vin_uv_f ault occurs, the input voltage must rise above vin_uv_warn_limit to clear the fault, which provides hysteresis to the fault threshold. in response to the uv_warn_limit being exceeded, the device: sets the none of the above and input bits in status_word, sets the vin_uv_warning bit in status_input, and notifies the host. data length in bytes: 2 data format: linear-11 type : r/w default value: 1.1 x vin_uv_fault_limit pin-strap setting units: v range : 0v to 12v vin_uv_fault_limit (59h) definition: sets the v in undervoltage fault threshold. data length in bytes: 2 data format: l11 type: r/w default value: pin-strap setting units: v range: 0v to 12v settings actions 80h disable with no retry bfh disable and continuous retry with 70ms delay ISL8277M fn8923 rev.1.00 page 36 of 57 aug 17, 2017 vin_uv_fault_response (5ah) definition: configures the v in undervoltage fault response as defined by the followin g table. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a power_good_on (5eh) definition: sets the voltage threshold for power-good indication . power-good asserts when the output voltage exceeds power_good_on and de-asserts when the output voltage is less than vout_uv_fault_limit. data length in bytes: 2 data format: l16u type: r/w default value: 0.9xvout_command pin-strap setting units: v ton_delay (60h) definition: sets the delay time from when the device is enabled to the start of v out rise. data length in bytes: 2 data format: l11 type: r/w default value: ca80h, 5 ms units: ms range: 0 to 500ms ton_rise (61h) definition: sets the rise time of v out after enable and ton_delay. data length in bytes: 2 data format: l11 type: r/w default value: ca80h, 5 ms units: ms range: 0 to 200ms toff_delay (64h) definition: sets the delay time from disable to start of v out fall. data length in bytes: 2 data format: l11 type: r/w default value: ca80h, 5 ms units: ms range: 0 to 500 seconds settings actions 80h disable with no retry bfh disable and continuous retry with 70ms delay ISL8277M fn8923 rev.1.00 page 37 of 57 aug 17, 2017 toff_fall (65h) definition: sets the fall time for v out after disable and toff_delay. data length in bytes: 2 data format: l11 type: r/w default value: ca80h, 5 ms units: ms range: 0 to 200ms status_byte (78h) definition: returns one byte of information with a summary of the most critical faults. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a bit number status bit name meaning 7 busy a fault was declared because the device was busy and unable to respond. 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory, or logic fault has occurred. 0 none of the above a fault or warning not listed in bits 7:1 has occurred. ISL8277M fn8923 rev.1.00 page 38 of 57 aug 17, 2017 status_word (79h) definition: returns two bytes of information with a summary of the unit's fault condition. based on the information in these bytes, the host can get more information by reading th e appropriate status registers. the low byte of the status_word is the same register as the status_byte (78h) command. data length in bytes: 2 data format: bit type: read only default value: 0000h units: n/a status_vout (7ah) definition: returns one data byte with the status of the output voltage. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a bit number status bit name meaning 15 vout an output voltage fault or warning has occurred. 14 iout/pout an output current or output power fault or warning has occurred. 13 input an input voltage, input current, or input power fault or warning has occurred. 12 mfg_specific a manufacturer specific fault or warning has occurred. 11 power_good# the power_good signal, if present, is negated. 10 fans a fan or airflow fault or warning has occurred. 9 other a bit in status_other is set. 8 unknown a fault type not given in bits 15:1 of the status_word has been detected. 7 busy a fault was declared because the device was busy and unable to respond. 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0 none of the above a fault or warning not listed in bits 7:1 has occurred. bit number status bit name meaning 7 vout_ov_fault indicates an output overvoltage fault. 6 vout_ov_warning indicates an output overvoltage warning. 5 vout_uv_warning indicates an output undervoltage warning. 4 vout_uv_fault indicates an output undervoltage fault. 3:0 n/a these bits are not used. ISL8277M fn8923 rev.1.00 page 39 of 57 aug 17, 2017 status_iout (7bh) definition: returns one data byte with the status of the output current. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a status_input (7ch) definition: returns input voltage and input current status information. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a status_temp (7dh) definition: returns one byte of information with a summary of any temperature related faults or warnings. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a bit number status bit name meaning 7 iout_oc_fault an output overcurrent fault has occurred. 6 iout_oc_lv_fault an output overcurrent and low voltage fault has occurred. 5 iout_oc_warning an output overcurrent warning has occurred. 4 iout_uc_fault an output undercurrent fault has occurred. 3:0 n/a these bits are not used. bit number status bit name meaning 7 vin_ov_fault an input overvoltage fault has occurred. 6 vin_ov_warning an input overvoltage warning has occurred. 5 vin_uv_warning an input undervoltage warning has occurred. 4 vin_uv_fault an input undervoltage fault has occurred. 3:0 n/a these bits are not used. bit number status bit name meaning 7 ot_fault an over-temperature fault has occurred. 6 ot_warning an over-temperature warning has occurred. 5 ut_warning an under-temperature warning has occurred. 4 ut_fault an under-temperature fault has occurred. 3:0 n/a these bits are not used. ISL8277M fn8923 rev.1.00 page 40 of 57 aug 17, 2017 status_cml (7eh) definition: returns one byte of information with a summary of any communications, logic, and/or memory errors. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a status_mfr_specific (80h) definition: returns one byte of information providing the status of the device's voltage moni toring and clock synchronization faults. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a read_vin (88h) definition: returns the input voltage reading. data length in bytes: 2 data format: l11 type: read only units: v read_vout (8bh) definition: returns the output voltage reading. data length in bytes: 2 data format: l16u type: read only units: v bit number meaning 7 invalid or unsupported pmbus command was received. 6 the pmbus command was sent with invalid or unsupported data. 5 packet error was detected in the pmbus command. 4:2 not used. 1 a pmbus command tried to write to a read only or protected command, or a communication fault other than the ones listed in this table has occurred. 0not used. bit number field name meaning 7:6 reserved 5 vmon uv warning the voltage on the vdrvout pin has dropped below 4.4v. 4 vmon ov warning the voltage on the vdrvout pin has risen above 5.5v. 3 external switching period fault loss of external clock synchronization has occurred. 2 reserved 1 vmon uv fault the voltage on the vmon pin has dropped below the level set by vmon_uv_fault. 0 vmon ov fault the voltage on the vmon pin has risen above the level set by vmon_ov_fault. ISL8277M fn8923 rev.1.00 page 41 of 57 aug 17, 2017 read_iout (8ch) definition: returns the output current reading. data length in bytes: 2 data format: l11 type: read only default value: n/a units: a read_internal_temp (8dh) definition: returns the controller juncti on temperature reading from internal temperature sensor. data length in bytes: 2 data format: l11 type: read only units: c read_external_temp (8eh) definition: returns the temperature reading from the extern al temperature device connected to xtemp pins. data length in bytes: 2 data format: l11 type: read only units: c read_duty_cycle (94h) definition: reports the actual duty cycle of the converter during the enable state. data length in bytes: 2 data format: l11 type: read only units: % read_frequency (95h) definition: reports the actual switching frequency of the converter during the enable state. data length in bytes: 2 data format: l11 type: read only units: khz mfr_id (99h) definition: sets user defined identification. the sum total of char acters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per comm and cannot exceed 128 characters. this limitation includes multiple writes of this command before a store command. to clea r multiple writes, perform a rest ore, write this command, then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a ISL8277M fn8923 rev.1.00 page 42 of 57 aug 17, 2017 mfr_model (9ah) definition: sets a user defined model. the sum total of characte rs in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per comm and cannot exceed 128 characters. this limitation includes multiple writes of this command before a store command. to clea r multiple writes, perform a rest ore, write this command, then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a mfr_revision (9bh) definition: sets a user defined revision. the sum total of characte rs in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per comm and cannot exceed 128 characters. this limitation includes multiple writes of this command before a store command. to clea r multiple writes, perform a rest ore, write this command, then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a mfr_location (9ch) definition: sets a user defined location identifier. the sum tota l of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per command cannot ex ceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command then, perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a mfr_date (9dh) definition: sets a user defined date. the sum total of characters in mfr_id, mfr_model, mfr_revi sion, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of this command before a store command. to clear multiple wr ites, perform a restore, write this command, then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a reference: n/a mfr_serial (9eh) definition: sets a user defined serialized identifier. the sum to tal of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per command cannot ex ceed 128 characters. this limitation includes multiple writes of th is command before a store command. to clea r multiple writes, perform a restore, write this command, then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a ISL8277M fn8923 rev.1.00 page 43 of 57 aug 17, 2017 legacy_fault_group (a8h) definition: this command is used only when the power system is created by mixing the ISL8277M module with old generation digital modules (zl9101m, zl9117m, zl9006m, zl9010m) to power various rails. this command provides an ability to power down the system by broadcast faults between ol d and new generation digital modules. new generation module uses group id to broadcast faults betwee n each other. refer to ddc_group(e2h) command. old generation module uses rail id to broadcast fault. when new and old module s are mixed, ISL8277M can use group-id (new generation module) and/or rail-id (old generation module) to execute shutdown as resp onse to fault to selected group_ id or rail-id. a module can l isten to multiple rail-ids by writing 1 to a bit location representing rail-id of old generation modules. note; bit-5 in ddc_group command should be programmed 1 to activate fault broadcast. data length in bytes: 4 data format: bit type: r/w block default value: 00000000h units: n/a user_data_00 (b0h) definition: sets a user defined data. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one byte per command cannot exceed 128 characters. this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, write this command then perform a store/restore. data length in bytes: user defined data format: ascii type: block r/w default value: null units: n/a bit description bit description bit description bit description 31 listen to rail-31 23 listen to rail-2 3 15 listen to rail-15 7 listen to rail-7 30 listen to rail-30 22 listen to rail-22 14 listen to rail-14 6 listen to rail-6 29 listen to rail-29 21 listen to rail-21 13 listen to rail-13 5 listen to rail-5 28 listen to rail-28 20 listen to rail-20 12 listen to rail-12 4 listen to rail-4 27 listen to rail-27 19 listen to rail-1 9 11 listen to rail-11 3 listen to rail-3 26 listen to rail-26 18 listen to rail-18 10 listen to rail-10 2 listen to rail-2 25 listen to rail-25 17 listen to rail-17 9 listen to rail-9 1 listen to rail-1 24 listen to rail-24 16 listen to rail-16 8 listen to rail-8 0 listen to rail-0 ISL8277M fn8923 rev.1.00 page 44 of 57 aug 17, 2017 isense_config (d0h) definition: configures current sense circuitry. data length in bytes: 1 data format: bit type: r/w byte default value: 05h units: n/a user_config (d1h) definition: configures several user-level features. this command overrides the config pin settings. data length in bytes: 1 data format: bit type: r/w byte default value: 00h units: n/a bit field name value setting description 7:4 reserved 000 3:2 current sense blanking time 00 192ns sets the blanking time cu rrent sense blanking time. 01 256ns 10 412ns 11 640ns 1:0 current sense range 00 low range 25mv 01 mid range 35mv 10 high range 50mv 11 not used bit field name value setting description 7:5 reserved 0 reserved 4:3 ramp-up and ramp-down minimum duty cycle 00 0.39% sets the minimum duty-cycle during start-up and shutdown ramp. must be enabled with bit 10. 01 0.78% 10 1.17% 11 1.56% 2 minimum duty cycle control 0 disable control for minimum duty cycle. 1enable 1power-good pin configuration 0 open drain 0 = pg is an open-drain output. 1 = pg is a push-pull output. 1push-pull 0 xtemp enable 0 disable enable ex ternal temperature monitoring. 1enable ISL8277M fn8923 rev.1.00 page 45 of 57 aug 17, 2017 ddc_config (d3h) definition: configures ddc addressing. data length in bytes: 1 data format: bit type: r/w default value: 00h units: n/a power_good_delay (d4h) definition: sets the delay applied between the output exceeding the pg threshold (power_good_on) an d asserting the pg pin. the delay time can range from 0ms up to 500s, in steps of 125ns. a 1ms minimum configured value is recommended to apply proper de-bounce to this signal. data length in bytes: 2 data format: l11 type: r/w default value: 4ms units: ms range: 0 to 5s ascr_config (dfh) definition: allows user configurat ion of ascr settings. data length in bytes: 4 data format: cus type: r/w default value: 015a0100h bit field name value setting description 7:5 reserved 00 reserved reserved 4:0 rail id 0 to 31 (00 to 1fh) 0 configures ddc address bit purpose data format value description 31:25 unused 0000000h unused 24 asccr enable bit 1 enable 0 disable 23:16 ascr residual setting integer 15:0 ascr gain setting integer ISL8277M fn8923 rev.1.00 page 46 of 57 aug 17, 2017 sequence (e0h) definition: identifies the rail ddc id of the prequel and sequel rails wh en performing multi-rail sequencing. the device will enable its output when its en or operation enable states, as defined by on_off_config, are set and th e prequel device has issued a power-good event on the ddc bus. the device will disable its outp ut (using the programmed delay values) when the sequel device has issued a power-down event on the ddc bus. the data field is a two-byte value. the most significant byte contains the 5-bit rail ddc id of the prequel device. the least s ignificant byte contains the 5-bit rail ddc id of the sequel device. the most significant bit of each byte contains the enable of the preq uel or sequel mode. this command overrides the corresponding sequence configuration set by the config pin settings. data length in bytes: 2 data format: bit type: r/w default value: 0000h (prequel and sequel disabled) ddc_group (e2h) definition: configures fault spreading group id and enable, br oadcast operation group id and enable, and broadcast vout_command group id and enable. data length in bytes : 3 data format: bit type: r/w default value: 000000h (ignore broadcast vout_command and operat ion, sequence shutdown on power_fail event) bit field name value setting description 15 prequel enable 0 disable disable, no prequel preceding this rail. 1 enable enable, prequel to this rail is defined by bits 12:8. 14:13 reserved 0 reserved reserved 12:8 prequel rail ddc id 0-31 ddc id set to the ddc id of the prequel rail. 7 sequel enable 0 disable disable, no sequel following this rail. 1 enable enable, sequel to this rail is defined by bits 4:0. 6:5 reserved 0 reserved reserved 4:0 sequel rail ddc id 0-31 ddc id set to the ddc id of the sequel rail. bits purpose value description 23:22 reserved 0 reserved 21 broadcast_vout_command response 1 responds to broadcast_vout_command with same group id. 0 ignores broadcast_vout_command. 20:16 broadcast_vout_command group id 0-31d group id sent as data for broadcast broadcast_vout_command events. 15:14 reserved 0 reserved 13 broadcast_operation response 1 responds to broadcast_operation with same group id. 0ignores broadcast_operation. 12:8 broadcast_operation group id 0-31d group id sent as data for broadcast broadcast_operation events. 7:6 reserved 0 reserved 5 power_fail response 1 responds to power_fail events with same group id by shutting down immediately. 0 responds to power_fail events with same group id with sequenced shutdown. 4:0 power_fail group id 0-31d group id sent as data for broadcast power_fail events. ISL8277M fn8923 rev.1.00 page 47 of 57 aug 17, 2017 device_id (e4h) definition: returns the 16-byte (character) device identifier string. data length in bytes: 16 data format: ascii type: block read default value: part number/die revision/firmware revision mfr_iout_oc_fault_response (e5h) definition: configures the i out overcurrent fault response as defined by the following table. the command format is the same as the pmbus standard fault responses except that it sets the overcurrent status bit in status_iout. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable, and no retry) units: n/a mfr_iout_uc_fault_response (e6h) definition: configures the i out undercurrent fault response as defined by the foll owing table. the command format is the same as the pmbus standard fault responses except that it se ts the undercurrent status bit in status_iout. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a sync_config (e9h) definition: sets options for sync output configurations. data length in bytes: 2 data format: bit type: r/w default value: 00h settings actions 80h disable with no retry. bfh disable and continuous retry with 70ms delay. settings actions 80h disable with no retry. bfh disable and continuous retry with 70ms delay. settings actions 00h use internal clock. clock frequency is set by pin-strap or pmbus command. 02h use internal clock and output internal clock. 04h use external clock. ISL8277M fn8923 rev.1.00 page 48 of 57 aug 17, 2017 snapshot (eah) definition: a 32-byte read-back of parametric and status values. it allows monitoring and status data to be stored to flash following a fault condition. in case of a fault, the most recently updated values are stored to the flash memory. when snapshot status byte 22 is set stored, the device will no longer automatically capture parame tric and status values following a fault until stored data ar e erased. use the snapshot_control command to erase stored data and clear the status bit before the next ramp up. data erased is not allowed when the module is enabled. data length in bytes: 32 data format: bit field type: block read blank_params (ebh) definition: returns a 16-byte string indicating which parameter values we re either retrieved by the last restore operation or have been written since that time. re ading blank_params immediately after a restore operation allows the user to determine which parameters are stored in that store. a ?1? indicates the parameter is not present in the store and has not been written since t he restore operation. data length in bytes: 16 data format: bit type: block read default value: ff?ffh snapshot_control (f3h) definition: erases parametric and status values st ored at snapshot, flash memory location. data length in bytes: 1 data format: bit type: w byte byte number value pmbus command format 31:23 reserved reserved 00h 22 flash memory status byte ff - not stored 00 - stored n/a bit 21 manufacturer specific status byte status_mfr_specific (80h) byte 20 cml status byte status_cml (7eh) byte 19 temperature status byte status_temperature (7dh) byte 18 input status byte status_input (7ch) byte 17 i out status byte status_iout (7bh) byte 16 v out status byte status_vout (7ah) byte 15:14 switching frequency read_frequency (95h) l11 13:12 external temperature read_external_temp (8eh) l11 11:10 internal temperature r ead_internal_temp (8dh) l11 9:8 duty cycle read_duty_cycle (94h) l11 7:6 highest measured output current n/a l11 5:4 output current read_iout (8ch) l11 3:2 output voltage read_vout (8bh) l16u 1:0 input voltage read_vin (88h) l11 value description 03h erase parametric and status values stored in snapshot. ISL8277M fn8923 rev.1.00 page 49 of 57 aug 17, 2017 restore_factory (f4h) definition: restores the device to the hard-coded factory default values and pin-strap definitions. the device retains the default and user stores for restoring. security level is changed to level 1 following this command. data length in bytes: 0 data format: n/a type: write only default value: n/a units: n/a mfr_vmon_ov_fault_limit (f5h) definition: reads the vmon ov fault threshold. data length in bytes: 2 data format: l11 type: read only default value: cb00h (6v) units: range: 4v to 6v mfr_vmon_uv_fault_limit (f6h) definition: reads the vmon uv fault threshold. data length in bytes: 2 data format: l11 type: read only default value: ca00h (4v) units: v range: 4v to 6v mfr_read_vmon (f7h) definition: reads the vmon voltage. vmon is used to monitor vdrvout (p in 8) voltage through an internal 16:1 resistor divider. data length in bytes: 2 data format: l11 type: read only default value: n/a units: v range: 4v to 6v vmon_ov_fault_response (f8h) definition: reads the vmon ov fault response. data length in bytes: 1 data format: bit type: read only default value: 80h (disable and no retry) units: n/a vmon_uv_fault_response (f9h) definition: reads the vmon uv fault response. data length in bytes: 1 data format: bit type: read only default value: 80h (disable and no retry) units: n/a fn8923 rev.1.00 page 50 of 57 aug 17, 2017 ISL8277M intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at www.intersil.com . for a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary . you can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please visit our website to make sure you have the latest revision. date revision change aug 17, 2017 fn8923.1 added table 1 on page 3. changed the default value for 46h ?iout_oc _fault_limit? on page 24 to dbc0h, 30a. changed the default value for 4bh ?iout_uc_fault_limit? on page 24 to dc3fh, -30a. changed the type for f4h ?restore_factory? on page 26 to write block. changed the name of f5h ?vmon_ov_fault_limit? to ?mfr_vmon_ov_fault_limit? on page 27. changed the name of f6h ?vmon_uv_fault_limit? to ?mfr_vmon_uv_fault_limit? on page 27. changed the name of f7h ?read_vmon ? to ?mfr_read_vmon? on page 27. in table 5, changed the r set for the 5-5 entry to 13.3, 28.7, 61.9, or open. in table 8, changed the uvlo value for the last seven entries to 10.8 changed the default value for ?sync_config (e9h)? on page 47 from 0000h to 00h. changed the type for ?snapshot_control (f3h)? on page 48 from r/w byte to w byte. changed the range maximum for ?vout_max (24h)? on page 30 from 4v to 6v. changed the default value for ?vout_ov_warning_limit (42h)? on page 32 from 0.85 to 1.1. changed the default value for ?vout_uv_warning _limit (43h)? on page 32 from 0.85 to 0.9. updated table 7 on page 18 with new values. updated figures 10 through 15. updated table 2 on page 15 with new values. updated table 5 on page 18 with new values. updated table 7 on page 18 with new values. updated table 8 on page 19 with new values. changed the type for ?device_id? on page 26 from asc to ascii. updated the descriptions for bits 4 and 5 in ?status_mfr_specific? on page 25. feb 28, 2017 fn8923.0 initial release firmware revision history firmware revision code change description note isl8277-0-g0100 initial release ? copyright intersil americas llc 2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. ISL8277M fn8923 rev.1.00 page 51 of 57 aug 17, 2017 package outline drawing y41.17x19 41 i/o 17.0mm x 19.0mm x 3.6mm hda module rev 1, 5/16 2x 0.10 c 3.6 0.1 0.025 max // 0.10 c c side view 0.08 c seating detail a terminal #a1 index area b top view 0.20 ref 21 x 0.60 0.05 3 3 0.05 c terminal tip bottom view pin 1 indicator datum b datum a 0.30 ref see 0.30 ref 21 x 0.60 0.05 0.20 ref 1.00 bsc 1.00 bsc 2 2 detail a plane 2x 0.10 c 17.00 bsc 19.00 bsc a 18.50 0.15 16.50 0.15 m 0.10 c a b m 0.10 c a b 12.00 m 0.10 c a b m notes: 1. all dimensions a re in millimeters. 2. represents the basic land grid pitch. 3. the total number of i/o (excluding dummy pads). 4. unless otherwise specifi ed, tolerance: decimal 0.10. 5. dimensioning and tolerancing per asme y14.m-2009. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 2.975 1.350 0.20 ref 0.475 1.300 a b c d e f g h j k l m n p r t u v w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 9.00 for the most recent package outline drawing, see y41.17x19 . ISL8277M fn8923 rev.1.00 page 52 of 57 aug 17, 2017 size details for the 16 exposed daps bottom view 2.50 0.60 1.50 4x 0.60 0.80 2.00 0.70 0.70 1.30 0.60 1.00 0.60 1.00 0.60 0.60 1.60 2x 1.60 2x 0.60 1.50 0.60 0.80 5.10 7.60 4.90 2.00 8.20 8.20 5.10 1.50 1.80 3.00 1.50 1.40 2.00 2.70 3.05 4.80 5.80 10.00 3.00 3.50 4x 1.60 ISL8277M fn8923 rev.1.00 page 53 of 57 aug 17, 2017 size details for the 16 exposed daps top view 2.50 0.60 1.50 4x 0.60 0.80 2.00 0.70 0.70 1.30 0.60 1.00 0.60 1.00 0.60 0.60 1.60 2x 1.60 2x 0.60 1.50 0.60 0.80 5.10 7.60 4.90 2.00 8.20 8.20 5.10 1.50 1.80 3.00 1.50 1.40 2.00 2.70 3.05 4.80 5.80 10.00 3.00 3.50 4x 1.60 ISL8277M fn8923 rev.1.00 page 54 of 57 aug 17, 2017 recommended solder mask defi ned pcb land pattern (1) top view 0.00 0.000 0.000 0.000 8.500 8.200 7.050 6.850 6.700 5.700 5.300 4.700 4.300 3.700 3.300 2.700 2.300 1.700 1.300 0.700 0.300 0.300 0.700 1.300 1.700 2.300 2.700 3.300 3.700 4.300 4.700 5.300 5.700 6.700 8.300 8.500 0.775 0.175 6.300 7.700 9.500 9.300 8.700 8.300 7.700 7.300 6.700 6.300 5.700 5.300 4.700 4.300 3.700 3.300 2.700 0.044 0.556 0.400 1.400 2.000 6.150 7.575 7.775 5.900 7.900 8.500 9.200 9.500 1.000 2.675 3.275 4.625 8.500 8.300 7.600 7.400 5.550 5.350 5.100 4.900 3.500 3.000 2.800 1.600 0.200 1.400 1.600 3.000 4.700 6.350 6.550 8.200 6.300 1.000 2.700 1.400 8.500 9.500 9.200 7.300 7.100 5.200 5.000 3.100 2.900 1.000 0.300 1.450 1.650 3.400 3.600 5.350 5.550 7.300 8.700 9.300 9.500 8.300 7.700 5.900 7.450 7.650 4.400 5.400 4.025 0.600 ISL8277M fn8923 rev.1.00 page 55 of 57 aug 17, 2017 recommended solder mask defi ned pcb land pattern (2) top view 0.000 0.000 0.000 0.000 6.000 5.200 2.200 0.633 0.433 1.133 1.333 2.550 2.900 7.300 6.800 7.100 6.750 5.533 5.333 3.767 3.567 2.000 2.300 1.700 1.100 0.900 0.300 0.900 2.500 3.500 3.700 5.200 5.300 4.700 2.900 1.300 1.700 3.300 3.700 5.300 5.700 6.900 6.700 0.300 7.300 6.300 ISL8277M fn8923 rev.1.00 page 56 of 57 aug 17, 2017 recommended stencil pattern (90% paste to pad) (1) top view 0.000 0.000 0.000 0.000 8.500 8.180 7.070 6.830 5.720 5.280 4.720 4.285 3.715 3.285 2.715 2.285 1.715 1.285 0.715 0.285 0.285 0.715 1.285 1.715 2.285 2.715 3.285 3.715 4.285 4.715 5.285 5.715 6.285 6.720 8.280 8.500 6.740 7.715 0.760 0.190 9.500 9.280 8.720 8.280 7.720 7.285 6.715 6.285 5.715 5.285 4.715 4.285 3.715 3.285 2.715 1.420 5.940 6.180 7.545 7.805 7.860 8.530 9.170 9.500 0.980 0.420 0.536 0.024 8.500 8.270 7.630 7.370 6.960 5.580 5.320 5.140 4.860 3.530 3.040 0.040 1.360 1.640 2.960 4.740 6.310 6.590 8.160 8.500 5.380 4.420 2.680 1.420 9.500 8.720 7.720 7.260 5.590 3.640 3.360 1.690 1.410 0.260 1.040 2.860 3.140 4.960 5.240 7.060 7.340 9.160 8.285 6.320 5.310 0.585 1.980 8.280 0.015 ISL8277M fn8923 rev.1.00 page 57 of 57 aug 17, 2017 recommended stenci l pattern (90% paste to pad) (2 ) top view 0.000 5.970 5.230 2.160 0.673 0.393 1.093 1.373 2.533 2.860 6.330 8.270 7.270 7.730 2.270 1.730 0.930 1.070 0.270 0.870 3.740 5.160 4.610 4.040 3.260 2.690 2.770 1.630 1.370 0.230 1.015 1.585 5.730 7.270 5.270 3.730 3.270 1.730 1.270 0.270 6.733 5.573 5.293 3.807 3.527 2.040 2.940 4.660 6.660 6.940 5.340 8.260 6.330 6.830 7.060 2.530 3.470 5.930 7.420 7.680 9.170 |
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